Method of forming a transistor and structure therefor

ABSTRACT

In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

The present application is related to U.S. patent application Ser. No.13/590,947 entitled BIDIRECTIONAL FIELD EFFECT TRANSISTOR AND METHOD,having an attorney docket number of ONS01424, a common inventor, and acommon assignee, and which is hereby incorporated herein by reference.The present application is also related to a United States patentapplication having an attorney docket number of ONS01585 having commoninventors Balaji Padmanabhan et al. and a common assignee, which isfiled concurrently herewith and which is hereby incorporated herein byreference.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to electronics, and moreparticularly, to semiconductors, structures thereof, and methods offorming semiconductor devices.

In the past, the semiconductor industry utilized various differentdevice structures and methods to form metal oxide semiconductor (MOS)transistor. One particular structure for a vertical power MOS transistorutilized trenches that were formed in an active area of the transistor.A portion of the trenches were utilized as the gate regions of thetransistor. Some of these transistors also had a shield conductor thatassisted in lowering the gate-to-drain capacitance of the transistor.

One problem with the prior transistors was the switching speed.Typically, the shield conductor had a high resistance and also had ahigh capacitance that reduced the switching speed of the transistor.Additionally, it was more difficult to manufacture the shield conductorwhich increased the cost of the transistor.

Accordingly, it is desirable to have an MOS transistor that has a higherswitching frequency, that is easier to manufacture, and that has a lowercost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an enlarged cross-sectional view of an example of aportion of an embodiment of a semiconductor device in accordance withthe present invention;

FIG. 2-FIG. 6 illustrate various stages in portions of an example of anembodiment of a method of forming the semiconductor device of FIG. 1 inaccordance with the present invention;

FIG. 7 illustrates an enlarged cross-sectional view of anothersemiconductor device that is an alternate embodiment of thesemiconductor device described in the description of FIGS. 1-6 inaccordance with the present invention;

FIG. 8-FIG. 14 illustrate various stages in portions of an example of anembodiment of a method of forming the semiconductor device of FIG. 7 inaccordance with the present invention;

FIG. 15 illustrates an enlarged cross-sectional view of anothersemiconductor device that is an alternate embodiment of thesemiconductor device described in the description of FIGS. 1-14 inaccordance with the present invention;

FIG. 16-FIG. 22 illustrate various stages in portions of an example ofan embodiment of a method of forming the semiconductor device of FIG. 15in accordance with the present invention; and

FIG. 23 illustrates an enlarged cross-sectional view of the transistorof FIG. 2 taken across another cross-sectional region in accordance withthe present invention.

For simplicity and clarity of the illustration(s), elements in thefigures are not necessarily to scale, and the same reference numbers indifferent figures denote the same elements, unless stated otherwise.Additionally, descriptions and details of well-known steps and elementsare omitted for simplicity of the description. As used herein currentcarrying electrode means an element of a device that carries currentthrough the device such as a source or a drain of an MOS transistor oran emitter or a collector of a bipolar transistor or a cathode or anodeof a diode, and a control electrode means an element of the device thatcontrols current through the device such as a gate of an MOS transistoror a base of a bipolar transistor. Although the devices are explainedherein as certain N-channel or P-Channel devices, or certain N-type orP-type doped regions, a person of ordinary skill in the art willappreciate that complementary devices are also possible in accordancewith the present invention. One of ordinary skill in the art understandsthat the conductivity type refers to the mechanism through whichconduction occurs such as through conduction of holes or electrons,therefore, and that conductivity type does not refer to the dopingconcentration but the doping type, such as P-type or N-type. It will beappreciated by those skilled in the art that the words during, while,and when as used herein relating to circuit operation are not exactterms that mean an action takes place instantly upon an initiatingaction but that there may be some small but reasonable delay(s), such asvarious propagation delays, between the reaction that is initiated bythe initial action. Additionally, the term while means that a certainaction occurs at least within some portion of a duration of theinitiating action. The use of the word approximately or substantiallymeans that a value of an element has a parameter that is expected to beclose to a stated value or position. However, as is well known in theart there are always minor variances that prevent the values orpositions from being exactly as stated. It is well established in theart that variances of up to at least ten percent (10%) (and up to twentypercent (20%) for semiconductor doping concentrations) are reasonablevariances from the ideal goal of exactly as described. The terms first,second, third and the like in the claims or/and in the DetailedDescription of the Drawings, as used in a portion of a name of anelement are used for distinguishing between similar elements and notnecessarily for describing a sequence, either temporally, spatially, inranking or in any other manner. It is to be understood that the terms soused are interchangeable under appropriate circumstances and that theembodiments described herein are capable of operation in other sequencesthan described or illustrated herein. For clarity of the drawings, dopedregions of device structures are illustrated as having generallystraight line edges and precise angular corners. However, those skilledin the art understand that due to the diffusion and activation ofdopants the edges of doped regions generally may not be straight linesand the corners may not be precise angles.

In addition, the description illustrates a cellular design (where thebody regions are a plurality of cellular regions) instead of a singlebody design (where the body region is comprised of a single regionformed in an elongated pattern, typically in a serpentine pattern).However, it is intended that the description is applicable to both acellular implementation and a single base implementation.

DETAILED DESCRIPTION OF THE DRAWINGS

As will be seen further hereinafter, a semiconductor device is formed toinclude a semiconductor material of a first conductivity type having afirst surface and a second surface, and a first region of thesemiconductor material that includes a second doping type. A gatestructure of the device is formed in an opening that is in the firstregion with the opening extending into a portion of the semiconductormaterial that is underlying the first region. A gate conductor of thegate structure is within the opening. A gate insulator of the gatestructure has a first portion of the gate insulator positioned betweenthe gate conductor and a first portion of the semiconductor material. Ashield conductor of the gate structure is within the opening andoverlying the gate conductor. A shield insulator has a first portionpositioned between the shield conductor and the gate conductor with theshield insulator having a second portion positioned between the shieldconductor and a second portion of the gate insulator.

FIG. 1 illustrates an enlarged cross-sectional view of an example of aportion of an embodiment of an MOS transistor 50 that has an improvedswitching frequency, that is easier to manufacture, and that has a lowercost. Typically, transistor 50 includes an active region 51 and atermination region 52 that are illustrated in a general manner byarrows. A plurality of transistor cells are formed in the active regionand are interconnected together to function as one transistor. Examplesof the transistor cells are illustrated by transistor cells 55-57. Cells55-57 typically are formed in long stripes that would extendperpendicular to the plane of the page of FIG. 1. Cells 55-57 may haveother shapes in other embodiments such as a circular or other geometricshape. As is well known in the art, each of cells 55-57 function as asmall transistor and are interconnected together to form one largetransistor. As will be seen further hereinafter, in one embodiment,transistor 50 is formed as a vertical transistor that has lateralcurrent flow in a channel region of transistor 50 and may have verticalcurrent flow in other portions of transistor 50. This configurationassists in providing transistor 50 with a high operating frequency butstill with a low Rdson of a vertical transistor. Additionally,transistor 50 has a low resistance for a shield conductor of thetransistor which also improves the operating frequency of transistor 50.

Although the descriptions may focus attention on cells 56-57 and thenearby material, this is done for clarity of the descriptions and thoseskilled in the art will appreciate that the descriptions also apply toother cells of transistor 50 such as cell 55 and an adjacent cell (notshown) that may be positioned to the left of cell 55. As will be seenfurther hereinafter, each of cells 55-57 include a drain region, such asdrain regions 61 and 62 that are illustrated in a general manner byarrows, and a gate structure, such as a gate structure 63 of cell 57which is illustrated in a general manner by an arrow. Each gatestructure, such as gate structure 63 for example, includes a shieldconductor or shield, such as shields 88-90, overlying a gate conductoror gate, such as respective gates 80-82, with a shield insulator 85insulating each shield from the corresponding gate. Transistor 50 isdevoid of a shield conductor underlying any of gates 80-82 or positionedbetween any of gates 80-82 and the underlying channel region. Each ofthese features singularly and/or jointly facilitates forming a lowerresistance for the shield conductors which results in a higher operatingfrequency for transistor 50. Each of cells 55-57 also includes a sourceregion or source, such as sources 103 and 105 for example. A portion ofthe semiconductor material underlying regions 103 and/or 105 isconfigured to form a channel region of transistor 50, such as channelregions 59 and 60 which are illustrated in a general manner by arrows.The channel region of each cell underlies the corresponding gate, suchas channel region 59 underlying gate 82, so that current flows laterallythrough the channel region, as illustrated in a general manner by anarrow 64, between the source region and the drain region of each cell.Those skilled in the art understand that the direction of the current,thus the arrow, depends on whether it is a P-channel or an N-channeltransistor. Thus, the arrow may be opposite in other embodiments.

Transistor 50 may also include a gate contact structure 58 that isformed in region 52. Structure 58 may be formed in other areas indifferent embodiments, such as near a boundary with region 51. Thoseskilled in the art will understand that in most embodiments, gatecontact structure 58 does not extend out of the plane of the page ofFIG. 1 but that the illustrated view of structure 58 is at a pointtypically at the end of the trenches of gate structures 63. In otherembodiments, there may be multiple versions of structure 58. Thematerial of individual gates 80-83 typically are electrically connectedto material 78 of structure 58 at some point, and gates 80-83 are laterconnected to each other such as by metal connections or by otherconductors such as doped polysilicon.

FIG. 2-FIG. 6 illustrates various stages in portions of an example of anembodiment of a method of forming transistor 50. These descriptions havereferences to FIG. 1-FIG. 6. Although the descriptions of the methodsherein may focus attention on openings 72-73 and the nearby material,this is done for clarity of the descriptions and those skilled in theart will appreciate that the descriptions also apply to other cells oftransistor 50 such as cell 55 and an un-shown adjacent cell that may bepositioned to the left of cell 55.

Turning to FIG. 2, transistor 50 includes a semiconductor substrate 65which typically has a high doping concentration in order to form a lowresistance path for current flow for a vertical transistor. A layer 68of semiconductor material is formed on substrate 65. One example offorming layer 68 of semiconductor material on substrate 65 includesforming an epitaxial layer 66 on one surface or a first surface ofsubstrate 65 and forming an epitaxial layer 67 on layer 66. In otherembodiments, one of layers 66 or 67 may be omitted. In one embodiment,substrate 65 may be highly doped N-type material. In another embodiment,layer 66 may be heavily doped P-type material which forms a body regionfor transistor 50 and layer 67 could be P-type material in which thechannel region for transistor 50 is formed. In another embodiment,substrate 65 may be heavily doped P-type material and layer 66 may beomitted.

Openings 71-75 are formed to extend from a surface of layer 67 adistance 76 into layer 67. Distance 76 usually is chosen so thatopenings 71-74 extend through a semiconductor region 69. Openings 71-75may be formed by a variety of methods including applying a mask, notshown, on layer 67 and etching openings into the material of layer 67. Agate insulator 77 is formed along the bottom and at least a portion ofthe sidewalls of the openings. In another embodiment, insulator 77 isformed along all of the sidewall of the opening and also on the surfaceof layer 67. Insulator 77 may be formed by a variety of methods. Forexample, the mask may be removed after forming openings 71-75 and theexposed silicon surface may be oxidized or insulator 77 may be formed bydeposition techniques. In other embodiments, a portion of insulator 77may be formed by oxidation and another portion may be formed bydeposition.

A conductor material 78 is formed within openings 71-75. A portion ofthis conductor material will eventually form gates 80-83 within openings71-74. Typically, openings 71-75 are filled with a doped polysiliconmaterial. In other embodiments, a different conductor material may beused such as a silicide or a metal conductor.

In one embodiment, a portion of material 78 is removed from opening 75so that the top of material 78 is recessed slightly below the surface oflayer 67. In other embodiments, a portion of material 78 may be removedfrom all of openings 71-75 so that the top of material 78 is recessed inall of openings 71-75 as illustrated by dashed lines. In one embodiment,the portion of material 78 may be removed by applying a mask and etchingthe exposed portions of material 78.

Thereafter, semiconductor region 69 may be formed between the openingsthat are in active region 51 of transistor 50, such as between openings71-74. Portions of region 69 will eventually form the drain regions ofthe cells, thus, the drain region for transistor 50. Region 69 may beformed by a variety of methods. In the preferred embodiment, a portionof layer 67 is doped in order to form region 69 within a portion oflayer 67. In the preferred embodiment, transistor 10 is an N-channeltransistor, thus, region 69 is an N-type region.

In an alternate embodiment, region 69 may be formed prior to formingopenings 71-75. For example, an epitaxial layer may be grown on thesurface of layer 67 with the desired conductivity type of region 69 anda portion of the epitaxial layer external to openings 71-74 may becounter doped to provide the conductivity and doping that is desired forthe remainder of layer 67.

FIG. 3 illustrates a subsequent stage in an example of an embodiment ofa method of forming transistor 50. A second portion of material 78 isremoved from openings 71-74 leaving a third portion of material 78 nearthe bottom of openings 71-74 to form respective gates 80-83. Material 78typically is not removed from opening 75 in termination region 52,although it may also be removed in other embodiments. In one embodiment,the portion of material 78 is removed by applying a mask, not shown,that exposes openings 71-74 but not opening 75, and etching the exposedmaterial 78. In some embodiments, a protective layer may be includedabove material 78 in the event that excessive portions of insulator 77would be removed while removing the second portion of material 78. Theprotective layer may be silicon nitride or some other type of protectivematerial.

Subsequently, a shield insulator 85 is formed in openings 71-74 andoverlying respective gates 80-83 so that a portion of insulator 85 isbetween gates 80-83 and shield conductors 88-91 (see FIG. 1). Thethickness of insulator 85 typically is greater than the thickness ofinsulator 77 so that the thickness of the insulator between gates 80-83and shields 88-91 is thicker than the thickness of the gate insulatorportion of insulator 77 that underlies gates 80-83. In otherembodiments, insulator 85 may not be thicker than insulator 77. Inanother embodiment, the thickness of insulator 85 may be formed to havea thickness near the surface of region 69 and to decrease in thicknessas insulator extends into region 69 toward one of or each of gates80-83. One example embodiment is illustrated by gate structure 79,identified in a general manner by an arrow. The tapering of insulator 85will assist in selecting the doping concentration of layer 67 to achievelow Rdson. For example, insulator 85 may be tapered to have a thicknessthat decreases for at least a portion of a distance that insulator 85extends into region 69 or into opening 71. In other embodiments, thewidth of opening 71 may be formed to narrow as opening 71 extends intoregion 69. Although structure 79 is illustrated to have a taper thatextends away from a straight line at an angle, the taper could havevarious other shapes. For example, the taper may extend as a series ofsteps with rounded or rectangular corners, or may extend away with acurved shape. Additionally, the opening within insulator 85 may have adifferent such as closer to having straight sidewalls within theopening. In such an embodiment, the sidewalls of opening 71 may have asimilar taper so that the opening within insulator 85 has straightersidewalls or the thickness of insulator 77 may taper, or insulator 77may be omitted. In another embodiment, the sidewalls of structure 79 maybe formed to slope such as in a “V” shape or a “V” shape with aflattened bottom other shape where the sidewalls extend away from thesurface of region 69 at an angle other than ninety (90) degrees. Theshape of insulator 85 within opening 71 optionally may be used for anyof insulators 85. Although this optional embodiment is illustrated onlyin FIG. 3, it may be maintained as the shape of any or all of insulators85 for resulting transistor 50.

Insulator 85 usually is also formed on conductor 78 in opening 75. Inthe preferred embodiment, insulator 85 is formed by depositing a layerof tetraethyl orthosilicate glass (TEOS) and annealing it. Insulator 85may be other materials in other embodiments. Insulator 85 is formed ongates 80-83 and along the sidewalls of openings 71-74 leaving an opening86 in insulator 85. In other embodiments, insulator 85 may be formed byother techniques such as forming an insulator in the openings and thenetching another opening within the insulator. In other embodiments,insulator 85 may not be formed along the entire remaining length of thesidewall of the openings.

FIG. 4 illustrates transistor 50 at a subsequent stage in an example ofan embodiment of a method of forming transistor 50. Shield conductors88-91 are formed within openings 86 above respective gates 80-83. In oneembodiment, a layer of doped polysilicon is formed on insulator 85 andwithin openings 86 (such as illustrated by dashed line 87 in FIG. 3).Subsequently, the layer of doped polysilicon may be etched to remove thepolysilicon from the surface of transistor 50 and to remove a portion ofthe polysilicon material within openings 86 thereby recessing the top ofconductors 88-91 a distance 93 below the surface of insulator 85.Typically, the top of conductor 88-91 is at least no higher than thesurface of layer 67 but may be other heights in other embodiments.Subsequently, another insulator 92 may be formed in the remainder ofopenings 86 and on conductors 88-91 to cap the top of and insulate thetop of conductors 88-91. Insulator 92 usually is also formed overopening 75.

FIG. 5 illustrates transistor 50 at another subsequent stage in anexample of an embodiment of a method of forming transistor 50 wheretransistor 50 is prepared for forming source regions between every othercell such as between cells 56 and 57, and between cell 55 and theadjacent cell (not shown). A portion of the surface of region 69 isexposed between cells 56 and 57, thus, between openings 72-73. A mastersource region 97 is formed on the surface of layer 67 adjacent openings72-73 (and adjacent opening 77 and the adjacent opening, not shown). Inthe preferred embodiment, a portion of insulators 92, 85, and 77 areremoved in-between openings 72 and 73 to expose the surface of region69, illustrated by a dashed line 70. In one embodiment, a mask notshown, may be applied and patterned to expose the portion of insulator92 that is between openings 72 and 73. The mask opening may overlie aportion of insulator 92 and may also overlie a portion of insulator 77and 85 that is between shield conductors 88 and 89, as illustrated byvertical sides of dashed line 70. The exposed portion of insulators 92,85, and 77 are removed to form an opening 95. Opening 95 exposes thesurface of region 69 and adjacent portions of insulators 77 and 85. Inother embodiments, opening 95 may be formed to expose the surface ofregion 69 but not expose conductors 88-89. Subsequently, the exposedportions of insulators 92, 85, and 77 are etched through to remove theexposed portions thereof. Subsequently, the exposed portion of thesurface of region 69 is removed to expose the surface of layer 67 thatunderlies opening 95. Insulators 85 and 77 may form a portion of themask for this operation. In one embodiment, the material of region 69 isetched with a process that etches silicon but not the material used forinsulators 77, 85, and 92. In some embodiments, some portion of region69 may remain on the surface of layer 67 within opening 95.

The exposed portion of region 67 (and any remaining portion of region69) is doped to form master source region 97 on the surface of region67. Region 97 usually extends to abut insulators 77 on adjacent walls ofopening 72 and 73. In the preferred embodiment, the surface of region 67is doped, such as through an implant operation, so that region 97 has ahigher doping concentration and the same conductivity type as thematerial of region 69. Although region 97 is illustrated as notunderlying gates 81 or 82, in some cases the region 97 may diffuse tounderlie at least a portion of one of or both of gates 81-82.

FIG. 6 illustrates another stage in an example of an embodiment of amethod of forming transistor 50. An insulator 99 is formed withinopening 95 (FIG. 5) around the sidewalls of opening 95 so that anopening 101 is formed within insulator 99. Opening 101 exposes a portionof the surface of source region 97 (FIG. 5). In the preferredembodiment, insulator 99 is formed by depositing a TEOS layer, forexample by low-pressure chemical vapor deposition (LPCVD), so thatopening 101 is formed within the material formed for insulator 99. Inother embodiments, other techniques may be used to form insulator 99including forming a blanket insulator, forming opening 101 within theinsulator, and removing excess portions of the insulator that may be onthe lateral surface of transistor 50. A spacer etch process may be usedto remove horizontal portions of the insulator material used to forminsulator 99 thereby leaving the portions of insulator material withinopening 95 as insulator 99.

Opening 101 through insulator 99 exposes the surface of region 97.Opening 101 is extended by removing the exposed portion of region 97 andunderlying portions of layers 67 and 66 through opening 101. Opening 101is extended to extend at least through layers 66 and 67. In anembodiment for a vertical transistor, opening 101 could extend intosubstrate 65 in order to form a low resistance connection to the sourcefor transistor 50. Extending opening 101 through region 97 forms region97 into source regions or sources 103 and 105 so that cell 56 has source103 and cell 57 as source 105. Source 103 is proximal to gate 80.Alternately, source 103 may be formed adjacent to and spaced apart fromgate 80 at least by the distance of insulator 77.

Subsequently, a source conductor 108 may be formed within opening 101 sothat conductor 108 forms a low resistance ohmic electrical contact tosource regions 103 and 105, to layers 66 and 67, and optionally tosubstrate 65. Typically, conductor 108 fills opening 101. It ispreferable that the material used for conductor 108 is suitable to forma low resistance ohmic contact to both P-type and N-Type semiconductormaterial, this reduces the manufacturing costs for transistor 50.However, other methods may be used to form the ohmic contacts such asusing a highly doped contact region in one or all of the semiconductorregions that contact conductor 108. In one embodiment, tungsten is usedfor conductor 108. In the preferred embodiment, a titanium layer withtitanium nitride and tungsten fill material is used for conductor 108.Typically, the fill material is blanket deposited to fill opening 101and cover the surface of insulator 92. In other embodiments, otherconductors may be used as long as the conductor material forms an ohmiccontact to P-type and N-type semiconductor material. A planarizationstep may be used to substantially remove the material of conductor 108from the horizontal surface of insulator 92.

Referring back to FIG. 1, the source conductor is enlarged to also forman ohmic electrical connection to shield conductors 89-90. Also, drainconductors 113 and 115 are formed for transistor 50. Drain contactregions 112 and 114 may be formed in respective drain regions 61 and 62of the material of region 69 to facilitate forming a low resistanceelectrical contact to the material of region 69 that forms drain regions61 and 62. Openings may be formed through insulators 92, 85, and 77overlying the portion of the material of region 69 that forms drainregions 61 and 62. Openings may also be formed at the same time forforming conductor 119 and for enlarging source conductor 108 to includeadditional source conductor portion 118. The opening for portion 118should be sufficient to expose a portion of shield conductors 88 and 90and a portion of conductor 108. For example, a mask may be applied toinsulator 92 and patterned with openings that overlie the selectedlocations. The underlying portions of insulators 92, 85, and 77 may beremoved from the openings.

The exposed surface of region 69 may be doped to form highly doped draincontact regions 112 and 114 within respective drain regions 61 and 62 inorder to facilitate forming an ohmic contact to the material of region69. In an optional embodiment, another mask may or may not be used toblock the dopants from the openings that were formed for portion 118 andconductor 119. Optionally, material 78 within structure 58 may also bedoped to form a contact region as illustrated by dashed lines.

Subsequently, a conductor material may be applied to fill the openingsformed through insulators 92, 85, and 77 to enlarge source conductor 108to include portion 118 and to form drain conductors 113 and 115 andtermination conductor 119. Portion 118 forms an ohmic electrical contactto the material of shields 89 and 90 thereby forming a low resistanceelectrical connection between shields 89 and 90, source conductor 108,and sources 103 and 105. For the embodiment where conductor 108 contactssubstrate 65, the low resistance connection also includes substrate 65.The low resistance electrical connection reduces the shield electroderesistance of transistor 50 and reduces the shield capacitance whichimproves the switching frequency of transistor 50.

In the preferred embodiment, a drain electrode 120 may be formed tofacilitate electrically connecting the drain regions of transistor 50 toexternal connections such as package terminals or for connection toother devices. Also in the preferred embodiment, a source conductor 53may be applied to a second surface of substrate 65 to form transistor 50as a vertical transistor. For this configuration, conductor 53 forms alow resistance current flow path. Even in such a configuration, currentflow in the channel region is laterally underlying the gate conductorssuch as gates 80-82 as illustrated by arrow 64. For such aconfiguration, the source conductor of conductor 108 and portion 118still provide a low resistance connection to shield conductors 89-90.For other embodiments, such as for a lateral transistor configuration,conductor 53 may be omitted and a source electrode 122 may be formed tofacilitate electrically connecting the source regions of transistor 50to external connections such as package terminals or for connection toother devices.

In another embodiment, transistor 50 may be formed to have an even lowerRdson by omitting the portion of insulator 85 that is shown betweengates 80-83 and shields 88-91 such that shields 88-91 are electricallyconnected to gates 80-83, respectively. This configuration may reducethe Rdson but also may lower the switching frequency of transistor 50.

FIG. 7 illustrates an enlarged cross-sectional view of a transistor 150that is an alternate embodiment of transistor 50 that was explained inthe description of FIG. 1-FIG. 6. Transistor 150 includes an activeregion 151 and a termination region 152 that are similar to regions 51and 52 of transistor 50 and are illustrated in a general manner byarrows. A plurality of transistor cells 155-157 are similar to cells55-57 except that cells 155-157 have a source conductor 208 that isslightly different than source conductor 108 and have a gate structure163, illustrated in a general manner by an arrow, that has an insulatorconfiguration that is formed in a different manner than gate structure63. Transistor 150 has drain regions 161 and 162, illustrated in ageneral manner by arrows, that are similar to regions 61 and 62 oftransistor 50.

Gate structures 163 include a shield conductor or shield, such asshields 188-191 that are similar to shields 88-91, overlying a gateconductor or gate, such as gates 181-184 that are similar to respectivegates 80-83. Each of cells 155-157 also includes a source region, suchas source regions 203 and 205 for example that are similar to respectiveregions 103 and 105. The channel region of each cell underlies thecorresponding gate, such as channel region 159 underlying gate 183, sothat current flows laterally through the channel region. Although thedescriptions may focus attention on cells 156-157 and the nearbymaterial, this is done for clarity of the descriptions and those skilledin the art will appreciate that the descriptions also apply to othercells of transistor 150 such as cell 155 and an adjacent cell (notshown) that may be positioned to the left of cell 155.

FIG. 8-FIG. 14 illustrate various stages in portions of an example of anembodiment of a method of forming transistor 150. These descriptionshave references to FIG. 7-FIG. 14.

Referring now to FIG. 8, region 69 is formed prior to forming anyopenings within layer 68 of semiconductor material. During thisoperation, a first insulating layer 170 typically is formed on thesurface of region 69 and layer 67. Subsequently, a protective layer 176is formed on layer 170. The material of layer 176 is material that isnot etched by operations that etch layer 170. Another insulator layer179 is formed on layer 176. The material of layer 179 typically is amaterial that is not etched by operations that etch layer 176. In thepreferred embodiment, layer 176 is silicon nitride and layers 170 and179 are silicon dioxide (referred to as oxide). For example, layer 170may be an oxide layer that is formed during the formation of region 69.Layer 179 may be a layer of TEOS that is formed on layer 176. Thematerial of layers 170, 176, and 179 may be other insulating materialsin other embodiments. Layers 170, 176, and 179 will be used as ahard-mask or mask 169 for forming other elements of transistor 150.

Thereafter, openings 171-175 are formed through the layers of mask 169.Mask 169 is used to extend a depth of openings 171-175 into the materialof region 69. Typically, the process of extending the depth of openings171-175 causes a width 166 of openings 171-175 to be wider than thewidth of the opening formed through mask 169 so that openings 170-175undercut the semiconductor material from under a portion of layer 170.

A first insulator 177 is formed along the sidewalls and bottom ofopenings 171-175. Subsequently, a second insulator 178 may be formed oninsulator 177. In the preferred embodiment, insulator 177 is formed byoxidizing exposed portions of the semiconductor material within openings171-175 so that insulator 177 fills the space underlying layer 170.Insulator 178 may be formed by depositing insulator material withinopenings 171-175. For example insulator 178 may be formed from TEOS. Inanother embodiment, insulator 178 may be formed by depositing adifferent insulating material and forming an opening within the materialto retain an opening within insulator 178. As will be seen furtherhereinafter, insulators 177-178 form the gate insulator for transistorcells 155-157.

A conductor material 180 is formed within the remaining portions ofopenings 171-175. Conductor material 180 is similar to material 78.Portions of material 180 may be formed on the surface of mask 169 andmay be removed such as by CMP or an etching procedure or otherequivalent procedure. A portion of conductor material 180 may be removedin order to recess the top of material 180 within openings 171-175similarly to material 78 in FIG. 2. This procedure is mainly for opening175, therefore, in other embodiments openings 171-174 may not beaffected by this operation.

FIG. 9 illustrates a subsequent stage in the example of an embodiment ofa method of forming transistor 150. A portion of material 180 withinopenings 171-174 is removed to form gate conductors 181-184 withinrespective openings 171-174 and overlying portions of layer 67.Typically, a mask, not shown, is applied to protect opening 175 whilematerial 180 within openings 171-174 is removed through the openings inmask 169 to reduce the height of material 180 resulting in conductors181-184.

A shield insulator 185 is formed within openings 171-175. Insulator 185is formed similarly to insulator 85 that is explained in the descriptionof FIG. 3. Insulator 185 typically is also formed on material 180 withinopening 175. Shield conductors 188-191 are formed within the openings ofinsulator 185. Conductors 188-191 are formed similar to conductors 88-91that are explained in the description of FIG. 3-FIG. 4.

Subsequently, a shield cap 192 is formed within openings 171-174 toinsulate the top portions of conductors 188-191. Cap 192 may be formedby applying an insulator layer 193 (illustrated by a dashed line) ontomask 169 similar to insulator 92 that was explained in the descriptionof FIG. 4.

FIG. 10 illustrates transistor 150 at another subsequent stage. Portionsof insulator layer 193 that are not within openings 171-174 are removedalong with portions of insulator 185 and 179 that also are not withinopenings 171-174. During the process of removing the insulating layer toleave cap 192, the horizontal portions of insulator 185 and 179 orremoved to expose layer 176.

FIG. 11 illustrates another subsequent stage in the example of anembodiment of a method of forming transistor 150. Another insulatorlayer 194 is formed on layer 176 to assist in forming another hard maskor mask 201. The material for layer 194 is similar to the material usedfor insulator 185. An opening 195 is formed in the portion of layer 194that overlies the region where a source is to be formed for cells155-157. Opening 195 overlies the region between openings 172 and 173that overlies where sources 203 and 205 are to be formed. Opening 195also overlies at least a portion of both shields 189 and 190. Typically,a photomask, not shown, is pattern with an opening where opening 195 isto be formed, the exposed portions of layer 194 are removed, and thephotomask is subsequently removed. Thereafter, mask 201 is used toremove the exposed portions of layer 176, and the exposed portions oflayer 170 are removed to expose the surface of region 69 that is betweenopenings 172 and 173. The underlying portions of region 69 are alsoremoved to expose the surface of layer 67 in order to facilitate formingsource regions for transistor 150.

FIG. 12 illustrates another subsequent stage in the example of anembodiment of a method of forming transistor 150. A doped semiconductormaterial 196 is formed within opening 195. Material 196 does notnecessarily have to fill opening 195 but in some embodiments may fillopening 195 as illustrated in FIG. 12. Thereafter, dopants from material196 are diffused into layer 67 to form a master source region 197.Region 197 is formed adjacent to gate conductors 182-183 but separatedtherefrom by the gate insulator formed by insulators 177-178. Thoseskilled in the art understand that in another embodiment, the exposedportion of layer 67 (illustrated in FIG. 11) may be doped in order toform master source region 197 instead of forming region 197 from dopedconductor material 196. Alternately material 196 may be formed within aportion of opening 195 to form region 197, and thereafter, anothersemiconductor material may be used to fill the remainder of opening 195.

FIG. 13 illustrates another stage in the example of an embodiment of amethod of forming transistor 150. An opening 199 is formed throughmaterial 196 and to extend through region 197 and layers 67 and 66 toexpose the surface of substrate 65. In most embodiments, opening 199 mayextend a distance into substrate 65. Opening 199 separates region 197into two separate source regions 203 and 205 for respective cells 156and 157. A source conductor 208 is then formed within opening 199 toform an ohmic electrical connection to source regions 203 and 205 andlayers 66-67, and to substrate 65 for the embodiment where opening 199extends to substrate 65.

FIG. 14 illustrates another subsequent stage in the example of anembodiment of a method of forming transistor 150. Another opening 200may be formed to expose a top portion of conductors 189-190 and toremove the portion of insulators and 177, 178, and 185 that arelaterally between conductor 208 and adjacent conductors 189-190.

Referring back to FIG. 7, source conductor 208 is enlarged to include asource conductor portion 218 that expands conductor 208 to electricallyconnect to conductors 189-190. Additionally, openings may be formedoverlying a portion of drain regions 161 and 162 to facilitate formingdrain conductors 213 and 215 to the drain regions of cells 155-157.These openings may alternately be formed at the same time as openings200 or may be formed after forming portion 218. Conductors 213 and 215are similar to conductor 113 and 115 (FIG. 1) and may be formedsimilarly thereto. An additional opening may be formed overlyingmaterial 180 in termination region 152 to form electrical connectionthereto. In some embodiments, a drain contact region 211 may be formedwithin drain regions 161-162 to facilitate forming electrical connectionto the material and within region 69. The source conductor, includingconductor 208 and portion 218, forms a low resistance ohmic electricalconnection between sources 203 and 205 and respective shield conductors189 and 190.

FIG. 15 illustrates an enlarged cross-sectional view of a portion of anexample of an embodiment of a transistor 250 that is an alternateembodiment of transistors 50 and 150 that were explained in thedescription of FIG. 1-FIG. 14. Transistor 250 includes an active region251 and a termination region 252 that are similar to regions 151 and 152of transistor 150 and are illustrated in a general manner by arrows. Aplurality of transistor cells 255-257 are similar to cells 155-157except that cells 255-257 have a gate structure 263 that is formeddifferently. Cells 255-257 also have a source conductor 308 is slightlydifferent than source conductors 108 and 208. Transistor 250 has drainregions 261 and 262, illustrated in a general manner by arrows, that aresimilar to regions 161 and 162 of transistor 150.

Gate structures 263 include a shield conductor or shield, such asshields 288-291 that are similar to shields 188-191, overlying a gateconductor or gate, such as gates 281-284 that are similar to respectivegates 181-184. Each of cells 255-257 also includes a source region, suchas source regions 303 and 305 for example that are similar to respectiveregions 203 and 205 of transistor 150. Although regions 303 and 305 areillustrated as not underlying gates 281 or 282, in some cases region 303and/or 305 may diffuse to underlie at least a portion of one of or bothof gates 281-282. The channel region of each cell underlies thecorresponding gate, such as channel region 259 underlying gate 283, sothat current flows laterally through the channel region. Although thedescriptions may focus attention on cells 256-257 and the nearbymaterial, this is done for clarity of the descriptions and those skilledin the art will appreciate that the descriptions also apply to othercells of transistor 250 such as cell 255 and an adjacent cell (notshown) that may be positioned to the left of cell 255.

FIG. 16-FIG. 22 illustrates various stages in portions of an example ofan embodiment of a method of forming transistor 250. These descriptionshave references to FIG. 15-FIG. 22.

Referring now to FIG. 16, region 69 is formed prior to forming anyopenings within layer 68 of semiconductor material. During thisoperation, a first insulating layer 270 typically is formed on thesurface of region 69 and layer 67. Subsequently, a protective layer 276is formed on layer 270. Another insulator layer 286 is formed on layer276. The material and methods for forming layers 270, 276, and 279 aresimilar to respective layers 170, 176, and 179 of FIG. 8. Layer 286preferably is formed from silicon dioxide but may be other materials inother embodiments such as silicon nitride of other equivalent material.The thickness of layer 286 generally is greater than the thickness oflayers 270 and/or 276. Layers 270, 276, and 286 will be used as ahard-mask or mask 269 for forming other elements of transistor 250.Openings are formed through layer 286 overlying openings 271-275,however, the openings in layer 286 generally have a greater width thanopenings 271-275 through mask 269.

Thereafter, openings 271-275 are formed through the layers of mask 269in a manner similar to forming respective openings 171-175 in thedescription of FIG. 8. Those skilled in the art will appreciate that theprocess of forming openings 271-275 may result in forming openings271-275 to have a greater width in the material of layer 286. Forexample, an isotropic etch may be used on layer 286 which may cause theresulting openings in layer 286 to have a greater width than openings271-275 through mask 269. A first insulator 277 and an optional secondinsulator 278 may be formed in openings 271-275 in a manner similar toinsulators 177 and 178 in the description of FIG. 8. As will be seenfurther hereinafter, insulators 277-278 form the gate insulator forcells 255-257. Insulator 278 may be used if it is desirable to increasethe thickness of the gate insulator of transistor 250. Those skilled inthe art will appreciate that the material of layer 278 may extend alongthe top of layer 286 and along the sidewalls of openings 271-275.Openings 271-273 have a width 266 that is similar to width 166 (FIG. 8).

FIG. 17 illustrates a subsequent stage in the example of an embodimentof a method of forming transistor 250. A conductor material 280 isformed within the remaining portions of openings 271-275 including theopenings formed in layer 286. Conductor material 280 and the formationmethod is similar to material 180 that was described in the descriptionof FIG. 8. However, material 280 is not removed from within openings271-275 at this step in the method. The portion of material 280 in theopenings within layer 286 forms a cap 287 at the top of material 280. Inother embodiments, portions of material 280 may be formed on the surfaceof layer 286 and may be removed such as by CMP or an etching procedureor other equivalent procedure.

FIG. 18 illustrates a subsequent stage in the example of an embodimentof a method of forming transistor 250. The material of layer 286 andunderlying portions of layer 278 are removed which exposes cap 287 ofconductor material 280. Portions of layer 278 that underlie cap 287typically remains. In some embodiments, the removal step may reduce thethickness of caps 287. Subsequently, another insulator layer orinsulator 298 is formed on caps 287 to protect material 280 insubsequent operations. The step of forming insulator 298 may also formportions of layer 298 on the surface of layer 276. In other embodiments,layer 276 may be blocked from the material of insulator 298.

FIG. 19 illustrates another subsequent stage in the example of anembodiment of a method of forming transistor 250. Optionally, anotherinsulator layer 279 may be formed on the surface of layer 276 to protectthe top of layer 278 from subsequent operations. An opening 295 isformed in the portion of insulator 298 and underlying layers thatoverlies the region where a source is to be formed for cells 255-257.Opening 295 exposes the surface of region 69 that is between openings272 and 273. Opening 295 overlies the region between openings 272 and273 that overlies where sources 303 and 305 are to be formed. Typically,a photomask, not shown, is patterned with an opening where opening 295is to be formed, and the exposed portions of layer 279 is removed. Sincelayers 279 and 276 generally are different materials, a separate step istypically used to remove the underlying portion of layer 276. Anotherstep may be used to remove the underlying portions of layer 270 andexpose the underlying surface of region 69. Opening 295 facilitatesforming self-aligned source regions and source conductors for transistor250.

The exposed portion of region 69 is removed to extend opening 295through region 69 and expose the surface of layer 67. In someembodiments, opening 295 may extend into layer 67 and in otherembodiments a portion of region 69 may remain in opening 295. Thephotomask may subsequently be removed.

FIG. 20 illustrates another subsequent stage in the example of anembodiment of a method of forming transistor 250. A doped semiconductormaterial 296 is formed within opening 295. In the preferred embodiment,material 296 is doped polysilicon but may be other types ofsemiconductor material that can be used to diffuse dopants into otherregions. Material 296 is formed on the bottom of opening 295 and in someembodiments on the sidewalls of opening 295. In other embodiments, aportion of material 296 may also be formed on insulator 298. Material296 typically is formed as a layer on the sidewalls and bottom ofopening 295 and typically does not fill opening 295. In some embodimentsmaterial 296 may fill opening 295 as illustrated by material 196 of FIG.12. Those skilled in the art will appreciate that some portions ofmaterial 296 may also be formed on the surface of layer 279 and layer298 as illustrated. In other embodiments, those portions may be blockedfrom material 296 such as by a mask or other manner. Thereafter, dopantsfrom material 296 are diffused into layer 67 to form a master sourceregion 297 on the surface of layer 67. Region 297 is similar to region197 described in the description of FIG. 12. Although region 297 isillustrated as not underlying any of gate structures 263, in some casesregion 297 may diffuse to underlie at least a portion of one of or bothof the adjacent structures 263.

FIG. 21 illustrates another subsequent stage in the example of anembodiment of a method of forming transistor 250. An opening 299 isformed to extend through region 297 and layers 67 and 66 to expose thesurface of substrate 65. In most embodiments, opening 299 may extend adistance into substrate 65. Opening 299 typically is narrower than thewidth of opening 295, such as by the thickness of material 296. Opening299 separates region 297 into two separate source regions 303 and 305for respective cells 256 and 257.

Subsequently, all portions of material 296, insulator 298, and layer 279that are overlying layer 276 are removed. Caps 287 are also removed, asillustrated by dashed lines. Typically, material 296, insulator 298, andlayer 279 are removed and a separate operation is used to remove caps287. For example, an etching operation that stops on the material oflayer 276 may be used to remove material 296, insulator 298, and layer279. Caps 287 may then be removed by CMP or etching or other similartechniques.

Opening 299 separates region 297 into two separate source regions 203and 205 for respective cells 256 and 257. A source conductor 308 is thenformed within opening 299 to form an ohmic electrical connection tosource regions 303 and 305 and layers 66-67, and to substrate 65 for theembodiment where opening 299 extends to substrate 65. Conductor 308 issimilar to conductor 208 (FIG. 14).

FIG. 22 illustrates another subsequent stage in the example of anembodiment of a method of forming transistor 250. Remaining portions ofgate structures 263 are formed. A portion of material 280 withinopenings 271-274 is removed to form gate conductors 281-284 withinrespective openings 271-274 and overlying portions of layer 67. Theremoval operation may be similar to the removal operation explained inthe description of FIG. 9 for material 180. A shield insulator 285 isformed within openings 271-275 in a manner similar to insulator 185(FIG. 9). Insulator 285 typically is also formed on conductors 308, onlayer 276, and on material 280 within opening 275. Shield conductors288-291 are formed within the openings of insulator 285. Conductors288-291 are formed similar to conductors 188-191 that are explained inthe description of FIG. 9. However, none of the material of conductors288-291 is removed after forming conductors 288-291.

Referring back to FIG. 15, an opening may be formed to expose a topportion of conductors 289-290 within gate structures 263 that areadjacent to source regions such as regions 303 and 305. The openingremoves the portion of insulators and 277, 278, and 285 that arelaterally between conductor 308 and adjacent conductors 289-290. Theopening may also remove a portion of conductor 308 that is adjacent tothe removed portions of the gate structures 263. Additional openings mayalso be formed to expose a portion of the surface of region 69 withinthe drain regions of transistor 250. In other embodiments, two differentoperations may be used to form the drain openings and the shieldconductor openings.

A conductor material is formed in the shield openings to enlarge sourceconductor 308 to include a source conductor portion 318 that expandsconductor 308 to electrically connect to conductors 289-290. Theconductor material may also be formed in the drain openings tofacilitate forming drain conductors 313 and 315 to the drain regions ofcells 255-257. These openings may alternately be formed at a differenttime from forming the shield conductor openings. Conductors 313 and 315are similar to conductor 213 and 215 (FIG. 7) and may be formedsimilarly thereto. An additional opening may be formed overlyingmaterial 280 in termination region 252 to form electrical connectionthereto. In some embodiments, a drain contact region also may be formedwithin drain regions 261-262 to facilitate forming electrical connectionto the material within region 69. The source conductor, includingconductor 308 and portion 318, forms a low resistance ohmic electricalconnection between sources 303 and 305 and respective shield conductors289 and 290.

FIG. 23 illustrates an enlarged cross-sectional view of transistor 50taken across the length of transistor 50 that extends out of the page ofFIG. 1. AS explained hereinbefore in the description of FIG. 1, thematerial of individual gates 80-83 typically are electrically connectedto material 78 of structure 58 at some point. FIG. 23 illustrates oneexample of an embodiment of a structure to electrically connect gates80-83 to material 78 of structure 58. In this example embodiment,material 78 of structure 58 extends to intersect the material of gates80-83 as illustrated by the electrical connection at the intersection ofmaterial 78 and gate 83. Those skilled in the art will appreciate thatthe material of gates 80-82 would extend parallel to gate 83 and alsoform an electrical connection therebetween, but can not be seen fromthis cross-section.

From all the foregoing, one skilled in the art will appreciate that inone embodiment, a transistor may comprise, a semiconductor substrate ofa first conductivity type, the semiconductor substrate having a firstsurface and a second surface;

a first semiconductor region, such as region 67 for example, having asecond conductivity type on the first surface of the semiconductorsubstrate;

a second semiconductor region, for example region 69, formed within thefirst semiconductor region wherein a portion of the first semiconductorregion underlies the second semiconductor region, the secondsemiconductor region having the first conductivity type;

a gate structure, such as gate structure 63 for example, formed in anopening, such as opening 73 for example, that extends from the secondsemiconductor region into the first semiconductor region;

a gate conductor, for example gate 82, of the gate structure formedwithin the opening and overlying a first portion, the region under gate82 for example, of the first semiconductor region;

a source region, such as region 205 for example, adjacent the gateconductor and spaced laterally, such as by insulator 77 for example,from the gate conductor;

a gate insulator, insulator 77 for example, between the gate conductorand the first portion of the first semiconductor region and between thesource region and the gate conductor wherein a channel region of thetransistor is in the first portion of the first semiconductor region sothat current flows laterally between the source region and under thegate structure;

a shield conductor, such as conductor 90 for example, overlying the gateconductor; and

a shield insulator, portion of insulator 85 between gate 82 and shield90 for example, between the gate conductor and the shield conductor.

In another embodiment the transistor may include that the gate structureis devoid of a shield conductor underlying the gate conductor, forexample devoid of a conductor that is electrically connected to shield90 either directly of connected via another conductor.

Another embodiment of the transistor may also include a source contactconductor, such as conductor 108 or 208 or 308 for example, extendingthrough the second semiconductor region and through the source regionand into the first semiconductor region to form an ohmic electricalconnection to the source region and the first semiconductor region.

In another embodiment, the transistor may include an insulator, such asinsulator 99 for example, positioned between a portion of the sourcecontact conductor that extends through the second semiconductor region.

Another embodiment of the transistor may include that the source regionis formed as a doped region on the surface of the first semiconductorregion.

The transistor may also include that the source contact conductordirectly contacts the source region and forms the ohmic electricalconnection thereto wherein the source region is devoid of a separatedoped contact region, for example devoid of a separate doped region thatfunctions as a contact region within the doped region of the sourceregion, positioned between the source contact conductor and the sourceregion.

Another embodiment of the transistor may include that the source contactconductor directly contacts the first semiconductor region and forms theohmic electrical connection thereto and wherein the first semiconductorregion is devoid of a separate doped contact region positioned betweenthe source contact conductor and the first semiconductor region.

The transistor may also include that the source contact conductor alsoforms an ohmic electrical contact to the shield conductor.

Another embodiment of the transistor may include that the gate insulatorabuts the shield insulator.

In another embodiment of the transistor, the shield conductor is formedwithin an opening that is formed to extend into the shield insulator.

Another embodiment of the transistor may include that the shieldinsulator is tapered to have a thickness that decreases for at least aportion of a distance into the semiconductor region increases.

In another embodiment the transistor may include that the shieldinsulator is tapered to have a thickness that decreases as the distanceinto the semiconductor region increases.

Those skilled in the art will also appreciate that an embodiment of asemiconductor device may comprise, a semiconductor material, such as thematerial of layer 67 for example, of a first conductivity type having afirst surface and a second surface;

a first region, such as region 69 for example, of the semiconductormaterial having a second conductivity type;

a gate structure, such as gate structure 63 or 163 or 263 for example,extending into the semiconductor material that is underlying the firstregion;

a gate conductor of the gate structure;

a gate insulator, such as insulator 77 for example, of the gatestructure having a first portion of the gate insulator positionedbetween the gate conductor and a first portion of the semiconductormaterial that underlies the gate conductor wherein the first portion ofthe semiconductor material is configured to form a channel region of thetransistor;

a shield conductor of the gate structure overlying the gate conductor;

a shield insulator having a first portion positioned between the shieldconductor and the gate conductor, the shield insulator having a secondportion positioned between the shield conductor and a second portion ofthe gate insulator; and

a third portion of the shield insulator overlying the shield conductor.

In another embodiment, the semiconductor device may include an openingextending from a surface of the first region into the semiconductormaterial with the gate insulator positioned on a bottom of the openingand the gate conductor within the opening and on the gate insulator.

Another embodiment of the semiconductor device may include a secondportion of the gate insulator positioned along a sidewall of the openingand abutting the shield insulator, for example the portion of insulator77 adjacent the sidewall of opening 74 and abutting shield 90 forexample.

The semiconductor device may also include that the shield conductor iswithin the opening, such as opening 74 for example, and overlying thegate conductor.

In another embodiment, the semiconductor device may also include asource region of the semiconductor device adjacent to and spaced apartfrom the gate conductor, such as spaced apart by the distance ofinsulator 77, and in another embodiment spaced laterally apart.

Those skilled in the art will also appreciate that a method of forming asemiconductor device may comprise,

providing a multi-layer semiconductor material, having a first layer ofa first conductivity type, such as layer 67 for example or layers 66 and67 for example or substrate 65 and layer 67 for example, having a firstregion, such as region 69 for example, of a second conductivity typeoverlying the first layer, having a plurality of openings, such asopenings 72 and 73 for example, that extend from a surface of the firstregion into the first layer wherein the plurality of openings havesidewalls, a gate insulator formed on the sidewalls of a first openingof the plurality of openings, and a gate conductor material within thefirst opening;

removing a first portion of the gate conductor material, such as theportion of material 78 above gate 82 for example, from the first openingand leaving a second portion of the gate conductor material within thefirst opening as a gate conductor wherein a portion of the first layerthat underlies the gate conductor, such as the portion underlying gate82 and insulator 77, forms a channel region of the semiconductor device;

forming a shield insulator within the first opening and overlying thegate conductor; forming a shield conductor overlying the gate conductor;and forming a source conductor, such as conductor 108 and extension 118for example, on a portion of the shield conductor to form an electricalconnection between the shield conductor and the first layer.

Another embodiment of the method may also include forming a sourceconductor to extend through the first region and into the first layerincluding forming the source conductor, such as one of conductors 108and/or 208, after forming the shield conductor, such as conductor 90,and before forming the electrical connection between the sourceconductor and the shield conductor.

The method may also include forming the shield insulator with a secondopening within the shield insulator, such as opening 86 for example,with at least a portion of the second opening, such as the sidewall ofthe second opening for example, extending substantially parallel to thesidewalls of the first opening, and forming the shield conductor withinat least a portion of the second opening.

Another embodiment of the method may include, forming a source region ofthe second conductivity type in the first layer and proximal to the gateconductor, such as adjacent to gate 82 and spaced apart by at least thedistance of insulator 77 for example.

The method may further include forming the source conductor toelectrically contact the source region.

In another embodiment, the method may also include forming the sourceconductor, such as conductor 308 for example, prior to removing thefirst portion of the gate conductor material from the first opening.

In view of all of the above, it is evident that a novel semiconductordevice and method is disclosed. Included, among other features, isforming a low resistance ohmic connection between the source conductorand the shield conductor which results in a low resistance for theshield conductor. The low resistance facilitates forming a higherswitching frequency for the transistor. Also included is forming thetransistor to have lateral current flow in the channel region whichresults in a shorter channel length which also improves the switchingfrequency.

While the subject matter of the descriptions are described with specificpreferred embodiments and example embodiments, the foregoing drawingsand descriptions thereof depict only typical and/or examples ofembodiments of the subject matter and are not therefore to be consideredto be limiting of its scope. It is evident that many alternatives andvariations will be apparent to those skilled in the art. Although theembodiment of a transistor 50 is used as a vehicle to explain thesubject matter of the invention, those skilled in the art willappreciate that alternatives are possible. Although the drain regionsare illustrated with wider spacing than the source regions, thoseskilled in the art will appreciate that the spacing may also besubstantially the same or the source spacing could be wider. The dopingof region 69 is selected such that when a drain-to-source voltage isapplied to transistor 50, drain regions 61-62 are substantially fullydepleted when the drain-to-source voltage reaches substantially thebreakdown voltage. In one embodiment, region 69 may have substantiallyuniform doping profile. In the preferred embodiment, the doping profilefor region 69 varies from heavily doped near the surface of region 69 tomore lightly doped near the interface with layer 67. Although thedevices are described as silicon semiconductor devices, those skilled inthe art understand that at least some elements herein, such as the gatestructures for example, are also applicable to devices using othersemiconductor materials such as gallium nitride (GaN).

As the claims hereinafter reflect, inventive aspects may lie in lessthan all features of a single foregoing disclosed embodiment. Thus, thehereinafter expressed claims are hereby expressly incorporated into thisDetailed Description of the Drawings, with each claim standing on itsown as a separate embodiment of an invention. Furthermore, while someembodiments described herein include some but not other featuresincluded in other embodiments, combinations of features of differentembodiments are meant to be within the scope of the invention, and formdifferent embodiments, as would be understood by those skilled in theart.

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 15. A method offorming a semiconductor device comprising: providing a multi-layersemiconductor material having a first layer of a first conductivitytype, having a first region of a second conductivity type overlying thefirst layer, having a plurality of openings that extend from a surfaceof the first region into the first layer wherein the plurality ofopenings have sidewalls, a gate insulator formed on the sidewalls of afirst opening of the plurality of openings, and a gate conductormaterial within the first opening; removing a first portion of the gateconductor material from the first opening and leaving a second portionof the gate conductor material within the first opening as a gateconductor wherein a portion of the first layer that underlies the gateconductor forms a channel region of the semiconductor device; forming ashield insulator within the first opening and overlying the gateconductor; forming a shield conductor overlying the gate conductor; andforming a source conductor on a portion of the shield conductor to forman electrical connection between the shield conductor and the firstlayer.
 16. The method of claim 15 further including forming a sourceconductor to extend through the first region and into the first layerincluding forming the source conductor after forming the shieldconductor and before forming the electrical connection between thesource conductor and the shield conductor.
 17. The method of claim 15wherein forming the shield insulator within the first opening includesforming the shield insulator with a second opening within the shieldinsulator with at least a portion of the second opening extendingsubstantially parallel to the sidewalls of the first opening, andforming the shield conductor within at least a portion of the secondopening.
 18. The method of claim 15 further including forming a sourceregion of the second conductivity type in the first layer and proximalto the gate conductor.
 19. The method of claim 18 further includingforming the source conductor to electrically contact the source region.20. The method of claim 15 further including forming a source conductorto extend through the first region and into the first layer includingforming the source conductor prior to removing the first portion of thegate conductor material from the first opening.